1. Field of the Invention
The present invention is directed to a capacitor fabrication method of a semiconductor device, and in particular to a lower-portion electrode forming method of a capacitor in a semiconductor memory cell.
2. Description of the Background Art
In general, a semiconductor memory device includes a transistor for driving a memory operation and a capacitor for storing information in the form of an electrical change. Methods for increasing the capacitance of a memory cell capacitor in a Dynamic Random Access Memory (DRAM) device include extending an effective surface area of the capacitor by fabricating the capacitor in a three-dimensional shape, reducing the thickness of a dielectric, or increasing the dielectric constant. As the degree of integration of the DRAM device is increased, the process for extending the surface area of the capacitor or reducing the thickness of the dielectric becomes complicated, and further the reliability of such a process also declines. Therefore, endeavors to increase the volume of the effective electric charge on the capacitor by utilizing a dielectric film with a high dielectric constant, such as (Ba,Sr)TiO.sub.3 and (Pb,La)(Zr,Ti)O.sub.3 have been recently made. When a dielectric film with a high dielectric constant such as BST is directly deposited on a silicone (Si) substrate, the silicone is oxidized, and thus an electrical contact can become defective, or the BST thin film may be deteriorated due to the reactivity between BST and Si. Accordingly, it is necessary to form a metal thin film (lower-portion electrode) such as Pt, Ru and Ir at a lower portion of the dielectric film with a high dielectric constant such as BST.
FIG. 1 is a cross-sectional view illustrating the constitution of a capacitor in a conventional semiconductor memory device. A barrier layer 13 is formed on a silicone substrate 11 where a contact plug 12 is formed. A lower-portion electrode 15 of a material such as Pt, Ru and Ir is formed on an upper portion of the barrier layer 13. A dielectric film with a high dielectric constant is formed on the silicone substrate 11 including the lower-portion electrode 15. In the case that such a dielectric film with a high dielectric constant as BST is used in the fabrication of the capacitor, a memory device having a degree of integration over the giga-level can be fabricated without a complicated three-dimensional configuration for extending an effective area of the capacitor.
A Pt thin film is characterized by low reactivity and large working function. Accordingly, the Pt thin film is popularly used as the lower-portion electrode 15 with the dielectric film. However, as illustrated in FIG. 2, when the lower-portion electrode 15 consisting of a Pt thin film is formed, in case etching of the Pt thin film by using a photoresist film mask or an oxide film mask 19 is performed in accordance with the conventional art, a polymer 21 is formed at both sides of the lower-portion electrode 15. The polymer 21 is mostly a mixed residue of Pt, C and O. When etching of the Pt thin film is performed, the photoresist film or the oxide film being a material of the mask 19 is mixed with the Pt thin film, and then the polymer 21 is deposited at the side portions of the lower-portion electrode 15. It is considerably difficult to remove the polymer 21. Besides, when the dielectric film is directly deposited on the polymer 21, carbon and the like included in the polymer 21 react with the dielectric film. Consequently, the electrical characteristics are deteriorated. Further, the polymer 21 is a non-conductor, and thus the side portions of the capacitor electrode cannot be utilized. Therefore, there is a disadvantage in that the effective area of the entire capacitor is reduced.